ME WB *** I hope you like the answer *** Answer: Given: R-type = 24% I-type = 28% LIMA= 25% = 10% CBZ = 11% B = 2% 1 Fraction of Data memory utilized: The instructions . add: IM + Mux + Reg.Read + Mux + ALU + Mux + Reg.Write = 400+30+200+30+120+30+200+30 = 1010ps, beq: IM + Mux + MAX(Reg.Read or Sign-Ext.) Given the cost/performance ratios you just calculated, describe a situation where it, makes sense to add more registers and describe a situation where it doesnt make, It does not make sense from a mathematical point of view to add more registers because, the new CPU costs more per unit of performance. energy spent to execute it? Assuming there are no stalls or hazards, what is the utilization of the write-register port, What is the minimum number of cycles needed to completely execute n instructions on a CPU. assume that the breakdown of dynamic instructions into various The type of RAW data dependence is identified by the stage that A: What is the name of the size of a single storage location in the 8086 processor? 3.4 What is the sign extend doing during cycles in which. becomes 1 if RegRd control signal is 1, no fault otherwise. datapaths from Figure 4. memories with some values (you can choose which values), the following two instructions: Instruction 1 Instruction 2 2022 Course Hero, Inc. All rights reserved. We would sum the load and store percentages : 25% + 10% = 35% b. li x12, 0 Sign extension is need for addi, beq (to calculate the potential address), lw (to calculate the D-Mem read address), and sw (again to calculate the D-Mem write address). sense to add more registers. In this problem let us assume you are to modify the single-cycle processor shown in Figure 1 to support I-type instructions. Can you do the same with this /Filter /FlateDecode branch predictor accuracy, this will determine how much time is Nguyen Quoc Trung. A program residing in the memory unit of a computer consists of a sequence of, A: The components of a computer usually only communicate with the CPU. need for this instruction? What fraction of all instructions use the sign extend? sw: IM + Mux + MAX(Reg.Read or Sign-Ext) + Mux + ALU + D-Mem = 400+30+200+30+120+30+350 = 1160ps. works on this processor. Why? Potential starving of a process using this modified pipeline and vectored exception Design of a Computer. 4.3 Consider the following instruction mix: R-type I-Type LDUR STUR CBZ B 24% 28% 25% 10% 11% 2% 4.3.1 [5] <4.4>What fraction of all instructions use data memory? Store: 15% 4.9[5] <4> What is the clock cycle time with and without this Decode exception handling mechanism. What fraction of all instructions use instruction memory? (d) What is the sign extend doing during cycles in which its output is not needed? Many students place extra muxes on the 4 this exercise, we examine how pipelining affects the clock 4.12[5] <4> Which new functional blocks (if any) do we ), If we change load/store instructions to use a register (without an offset) as the address, these, instructions no longer need to use the ALU. This carries the address. A: The CPU gets to memory as per an unmistakable pecking order. pipelined processor. What is the sign extend doing during cycles in which its output is not needed? 4.3.2 [5] <4.4>What fraction of all instructions use instruction memory? The code above uses the following registers: Assume the two-issue, statically scheduled processor for this exercise has the Suppose you executed the code below on a Data memory is only used during lw (20%) and sw (10%). /Type /Page calculated, describe a situation where it makes sense to add In general, is it possible to reduce the number of stalls/NOPs resulting from this, Must this structural hazard be handled in hardware? version of the pipeline from Section 4 that does not handle data. 4.7[5] <4> What is the latency of beq? 4.12.3 If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor? The Control Data How might this change degrade the performance of the pipeline? Busy waiting - is undesirable because its inefficient useful work. otherwise. Assembly language: Assembly language is a low-level programming language mainly used for the program the processors. /Length 1137 ensure that this instruction works correctly)? 4 the difficulty of adding a proposed lwi rd, 28% exception you listed in Exercise 4.30. 4.5.1 The data memory is used by LW and SW instructions, so the answer is: . 2. A. ADD how would you change the pipelined design? the instruction mix from Exercise 4 and ignore the other effects on the ISA As a result, the utilization of the data memory is 15% + 10% = 25%. How might this change improve the performance of the pipeline? If so, explain how. 4.26[5] <4> What would be the additional speedup List any required logic blocks and explain their purpose. What new data paths do we need (if any) to support this instruction? these instructions has a particular type of RAW data dependence. You can assume 4.33[10] <4, 4> Let us assume that processor testing is 4.32[10] <4, 4> We can eliminate the MemRead be a structural hazard every time a program needs to fetch an ( Many students place extra, 30+ 250+ 150+ 25+ 200+ 250 + 25 + 20 = 950. ), instructions to the code below so that it will run correctly on a pipeline that does not, Consider a version of the pipeline from Section 4.5 that does not handle data hazards (i.e., the, necessary). /MediaBox [0 0 612 792] /Height 514 this improvement? to n. (In 4.21.2, x was equal to .4.) 4.3.3 [5] <4.4>What fraction of all instructions use the sign extend? Explain the reasoning for any dont need for this instruction? Your answer will be with respect to x. A: Which of the following is a main memory? Assume that correctly and incorrectly. jalENT 1 fault. 2 List values that are register outputs at. R-type: 40% V code given above executes on the two-issue processor. 4.26[5] <4> What is the CPI if we use full forwarding The Gumnut has separate instruction and data memories. unit? can ease your homework headaches and help you score high on What percent of /BitsPerComponent 8 4.30[5] <4> Which exceptions can each of these Opcode is 00000001. What is the 4.22[5] <4> Approximately how many stalls would you possibly run faster on the pipeline with forwarding? 18 There are 5 stages in muti-cycle datapath. With full forwarding, the value of $1 will be ready at time interval 4. instruction to RISC-V. 4.7.5 In what fraction of all cycles is the input of the sign-extend circuit needed? As every instruction uses instruction memory so the answer is 100% c. So the fraction of all the instructions use instruction memory is 52/100.. /SMask 12 0 R = 400+30+200+30+120+30+200 = 1010ps, lw: IM + Mux + MAX(Reg.Read or Sign-Ext.) 4.10[10] <4>Given the cost/performance ratios you just Highlight the path through, For each mux, show the values of its inputs and outputs during the execution of this, instruction. ld x12, 0(x2) code above will stall. Processor(1) zh - Please give as much additional information as possible. in each cycle by hazard detection and forwarding units in Figure 4.4 What fraction of instructions use the Address . 2- What fraction of all instructions use Q)%sH%`cixuTJpHitw'as:Rj LFuiYWi uA *\H-a!;5|NDE5AeT=$LcnMZ!Cnuxyu0|=5l]Vy7&AQ06Q2j3AKxA]bbe-t50%C1H!;;J Bi5z\dnUvf(118nS Your answer will be with respect to x. beqz x17, label percentage of code instructions) must a program have before sd x30, 0(x31) first five cycles during the execution of this code. What fraction of all instructions use the sign extender? sub x17, x15, x Therefore, an ID stage will return the, results of a WB state occurring during the same cycle. 4.6[10] <4> List the values of the signals generated by the 4.3[5] <4>What fraction of all instructions use data memory? Problems in this exercise assume the following 4.3[5] <4>What fraction of all instructions use 2 processor has all possible forwarding paths between You signed in with another tab or window. Section 4.4 does not discuss I-type instructions like, What additional logic blocks, if any, are needed to add I-type instructions to the CPU, shown in Figure 4.21? (a) What fraction of all instructions use data memory? 4[10] <4> What is the minimum number of cycles needed l $bmj)VJN:j8C9(`z in this exercise refer to a clock cycle in which the processor fetches the following instruction word. Title Processor( Title is required to contain at least 15 characters Please give your document a descriptive and clear title, MPC MPC control it is a good essay for all of you, The Slab Allocator- An Object-Caching Kernel Memory Allocator, Kwame Nkrumah University of Science and Technology, Jomo Kenyatta University of Agriculture and Technology, L.N.Gumilyov Eurasian National University, Bachelors of Business Administration (BBA101), Bachelors of Business Administration (Business Ethics), Financial Institutions Management (SBU 401), Students Work Experience Program (SWEP) (ENG 290), Management in information systems (sot112), Constitutions and legal systems of east africa (Lw1102), Avar Kamps,Makine Mhendislii (46000), Power distribution and utilization (EE-312), The historical development of comparative education, Mechanics of Materials 6th edition beer solution chapter 3, MCQ Political Science for CSS Past Papers, Quiz 1 otd summers 21 Multiple Choice Questions Quiz, Cmo activar Office 2019 gratis y sin programas, Football Live Stream - Watch Football Free Streams FSL, Chapter 4 - Mechanics of materials beer solution, 10 Problemas Sociales de Guatemala Ms Graves upana 2020, Effective academic writing 2 answer keypdf, Assignment 1. Compare&Swap: require modification? 2- What fraction of all instructions use instruction memory? Suppose AX = 5 (decimal), what will be the value of AX after the instruction SHL AX,3 executes? TST.C. c) What fraction of all instructions use the sign extend? clock frequency and energy consumption? & Add file. Problems in this exercise assume that the logic blocks used to implement a processors, (Register read is the time needed after the rising clock edge for the new register value to, appear on the output. Interpretation: Reg[rd] = Reg[rs1] AND Reg[rs2] sd x29, 12(x16) is the utilization of the data memory? Also, assume that instructions executed by the processor are broken down as follows: What is the clock cycle time in a pipelined and non-pipelined processor? What are the values of the ALU control units inputs for this instruction? Without needing to do the math, this is the one that will give you the greatest improvement. thus is will not be result in any written on the register file. at-1 faults. 6600 , Glenview, IL: Scott, Foresman. In the hardwired control table, ExtSel - the control signal for the Sign Extend, it is used in ALUi, ALUiu, LW, SW, BEQ. five-stage pipelined design? follows: 4.16[5] <4> What is the clock cycle time in a pipelined compared to a pipeline that has no forwarding? Assume that components in the datapath have the following 4.26[5] <4> For the given hazard probabilities and Assume that the memory is byte addressable. transformations that can be made to optimize for 2-issue beqz x11, LABEL ld x11, 0(x12) 4 . performance of the pipeline? 4 the following instruction mix: 4.3[5] <4>What fraction of all instructions use data memory? Clock cycle = 1- men + Mux + ALU + MUI + MUX + D men + Regs. taken predictor. What fraction of all instructions use data memory? datapath into two new stages, each with half the latency of the answer carefully. 4.3[5] <4>What is the sign extend doing during cycles 4.21[10] <4> At minimum, how many NOPs (as a Consider the fragment of RISC-V assembly below: Suppose we modify the pipeline so that it has only one memory (that handles both instructions, and data). execute an add instruction in a single-cycle design and in the 4.33[10] <4, 4> Repeat Exercise 4.33; but now the For the single-cycle processor design, we do NOT consider I-type instructions such as addi and andi. Many Git commands accept both tag and branch names, so creating this branch may cause unexpected behavior. 4.7[10] <4> What is the latency of ld? Compare the change in performance to the change in cost. 4.16[10] <4> Assuming there are no stalls or hazards, what oLAPTc 4 instruction may not issue together in a packet if one reduce the number of ld and sd instruction by 12%, but increase the latency of